TSMC's Capex Pivot: Why Deferring $410M Machines Could Be the Smartest Move in Semiconductors
Executive Summary
- ●TSMC is deferring ASML's $410M High-NA EUV machines through 2029 and redirecting capex toward CoWoS packaging — the actual binding constraint on AI chip supply.
- ●By skipping High-NA EUV, TSMC avoids $5–10B+ in tool costs while sustaining its technology lead via multi-patterning on existing EUV. Margins stay structurally above 65%.
- ●CoWoS capacity ramping from ~80K wafers/month to 115–140K (2026E) and ~260K (2028E). New Arizona packaging plant closes the loop for US-fabricated chips currently shipped back to Taiwan.
- ●ASE guides advanced packaging revenue to double in 2026. Fabless designers get packaging relief by 2027–2028.
Three Announcements in One Week Reveal a Deliberate Capital Reallocation
TSMC told the market three things over the past week. Taken individually, each is a routine corporate update. Taken together, they reveal a deliberate strategic pivot — one that has direct implications for margins, supply chain bottlenecks, and the investment case across the Taiwan semiconductor universe.
First, at its 2026 North America Technology Symposium on April 22, TSMC unveiled its A13 and A12 process nodes, both targeting volume production in 2029. Second, Deputy Co-COO Kevin Zhang confirmed TSMC will not deploy ASML's high numerical aperture (high-NA) EUV lithography machines — which cost upwards of €350 million ($410 million) apiece — through at least 2029. Third, TSMC broke ground on its first advanced packaging facility in Arizona, targeting CoWoS and 3D-IC capability before 2029.
The message: TSMC is redirecting capital from bleeding-edge lithography tools toward packaging infrastructure. In an environment where AI chip demand is supply-constrained by packaging, not transistor density, this is arguably the highest-ROI allocation decision in the semiconductor industry right now.
Record Q1 Earnings Validate the Demand Thesis Behind the Pivot
This comes one week after TSMC reported a record Q1 2026 — and the numbers deserve attention:
| Metric | 1Q26 | 4Q25 | YoY Change |
|---|---|---|---|
| Revenue | $35.9B | $33.7B | +40.6% |
| Net Income | $18.2B | $15.6B | +58% |
| Gross Margin | 66.2% | 62.3% | +3.9pp |
| HPC % of Revenue | 61% | 55% | +6pp |
| Advanced (≤7nm) % of Wafer Rev | 74% | 77% | -3pp |
| Sub-3nm % of Wafer Rev | 25% | 28% | -3pp |
Source: TSMC 1Q26 & 4Q25 Earnings Releases; CNBC; TrendForce
Note on node mix: The sequential dip in advanced/sub-3nm share from 4Q25 to 1Q26 reflects typical seasonal smartphone mix effects (iPhone ramp in 4Q), not a structural shift. HPC's rise to 61% of revenue — up 6pp QoQ — is the more telling signal, driven by AI accelerator demand.
Management raised full-year 2026 revenue guidance from "mid-20% growth" to above 30% YoY in USD terms and guided Q2 revenue of $39.0–$40.2B with gross margins of 65.5–67.5%. Capex guidance narrowed toward the high end of $52–56B, signaling conviction in demand visibility.
CEO C.C. Wei stated that "AI-related demand continues to be extremely robust" and cited strong customer signals reinforcing a "multi-year AI growth trend."
The stock reacted modestly — TSM is up ~14.5% over seven days but pulled back 1.3% intraday on April 23 as broader tech paused. Market cap sits at $1.9 trillion, making TSMC the world's 7th most valuable company.
Skipping $410M Machines Protects Margins Without Sacrificing Tech Leadership
ASML's high-NA EUV machines represent the next frontier in lithography — enabling finer patterning at sub-2nm nodes. But at $410M per tool, they are by far the most expensive equipment in semiconductor history. TSMC's decision to hold off through 2029 is not a signal of weakening AI demand. It's a statement about capital efficiency.
TSMC demonstrated at the symposium that its A13 process achieves 6% area savings and improved power efficiency versus A14 — without requiring high-NA EUV. The company is using existing EUV tools combined with multi-patterning techniques to push density gains, a strategy that preserves its technology lead while avoiding the depreciation drag of $410M tools that may not yet deliver commensurate yield improvements.
Margin implication: By deferring high-NA EUV adoption, TSMC avoids adding potentially $5–10B+ in tool costs to its capex base over 2026–2029. With gross margins already at 66.2% and guided to sustain above 65%, this decision provides a structural floor under margins even as total capex runs at $52–56B. Analyst consensus views this as a potential 1–2 percentage point gross margin tailwind versus a scenario where high-NA tools were deployed on schedule.
ASML read-through: ASML fell 3% on the news. The Dutch company targets €60B revenue by 2030, and TSMC — its largest customer — deferring high-NA adoption puts pressure on that timeline. ASML expects high-volume high-NA production in 2027–2028, but without TSMC as a launch customer, the ramp depends on Samsung and Intel, neither of which has TSMC's volume.
Packaging — Not Transistor Density — Is the Binding Constraint on AI Chip Supply Right Now
The real constraint in AI semiconductors today is not transistor density — it's packaging. Nvidia's H100, B100, and next-generation Rubin chips all require TSMC's CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging to integrate multiple compute dies with high-bandwidth memory (HBM). And CoWoS capacity has been the binding constraint on AI chip supply for over two years.
TSMC is aggressively expanding:
| CoWoS Metric | End-2024 | End-2025 | 2026E | 2027E | 2028E | 2029 |
|---|---|---|---|---|---|---|
| Reticle Size | — | — | 5.5x | — | 14x | >14x |
| Monthly Capacity (wafers) | ~35K | ~80K | 115–140K | ~170K | ~260K | — |
| Annual Capacity (wafers) | — | — | 1.28M | 2.49M | 3.15M | — |
| Integrated Components | — | — | — | — | ~10 compute dies + 20 HBM stacks | — |
Sources: TSMC Technology Symposium (April 22, 2026); TechNews via DQ India (institutional investor estimates for 2026E–2027E monthly); Goldman Sachs (annual capacity estimates, April 2026); Tom's Hardware (2024–2025 historical)
The 14-reticle CoWoS in 2028 is a step-change — nearly tripling the current 5.5x reticle size, enabling integration of approximately 10 large compute dies and 20 HBM stacks in a single package. TSMC also announced its 40-reticle System-on-Wafer-X technology for 2029, pushing toward wafer-scale integration.
The Arizona angle: Currently, chips fabricated at TSMC's Arizona fabs for Apple and Nvidia are shipped back to Taiwan for packaging — adding weeks of turnaround time and creating a geographic vulnerability. The new Arizona packaging plant (CoWoS + 3D-IC, targeting pre-2029) closes this loop. Amkor, the world's second-largest OSAT, is building its own Arizona packaging facility targeting early 2028 production, and TSMC has indicated ongoing collaboration with Amkor for customer overflow.
This is not just a supply chain efficiency play. With U.S. CHIPS Act subsidies flowing and geopolitical pressure mounting for domestic semiconductor self-sufficiency, packaging was the missing link. TSMC is filling it.
Supply Chain Winners and Losers: ASE Doubles Down, Delta Rides the Buildout, Fabless Designers Get Relief
ASE Technology (ASX US) — Direct Beneficiary. ASE, the world's largest outsourced semiconductor assembly and test (OSAT) provider, expects advanced packaging sales to double in 2026, with LEAP (Leading Edge Advanced Packaging) services projected to reach $3.2B (Source: ASE management, Seeking Alpha). As TSMC's internal CoWoS capacity remains fully allocated to tier-1 AI customers, overflow demand flows to ASE/SPIL. ASE is building a major new facility in Taiwan and its subsidiary SPIL recently held a grand opening for another new site. The packaging bottleneck is ASE's pricing power.
Delta Electronics (2308 TT) — Infrastructure Play. Every new fab and packaging facility requires power management and thermal solutions. Delta's Infrastructure segment — which includes ICT and energy infrastructure — generated NT$182B in FY2025 (~33% of total revenue), growing 82% YoY as AI-related power demand surged. AI power solutions alone represented ~25% of Delta's 2025 revenue. Delta doesn't disclose what share of revenue comes from semiconductor fabrication customers specifically, but its power systems and thermal management products are used across data centers and fab facilities alike. TSMC's Arizona expansion — now encompassing four wafer fabs plus a packaging facility — adds incremental demand, though the primary growth driver for Delta remains the broader AI data center buildout rather than fab construction alone.
MediaTek (2454 TT), Phison (8299 TT) — Indirect Beneficiaries. As CoWoS capacity expands, the packaging bottleneck eases for fabless designers. MediaTek's Dimensity AI chipsets and Phison's next-generation NAND controllers both require advanced packaging for AI-edge and data center applications. More packaging capacity = faster time-to-market for their designs.
Amkor Technology (AMKR US) — Companion Play. Amkor's Arizona facility targeting early 2028 production positions it as a complementary packaging provider for TSMC's US customers. Worth monitoring as a parallel beneficiary.
Sources: TSMC Q1 2026 Earnings Release & Call (April 16, 2026); TSMC 2026 NA Technology Symposium (April 22, 2026); Bloomberg (April 22, 2026); Reuters (April 22, 2026); CNBC (April 16, 2026); Seeking Alpha; SemiMedia (April 23, 2026); Taipei Times (April 24, 2026); DQ India citing TechNews; ASE management commentary via Seeking Alpha
Related Research
Nanya Tech Q1 2026: Legacy DRAM Squeeze Confirmed, and Three NAND Rivals Just Bought Equity to Secure Supply
Nanya's 67.9% gross margin on non-HBM DRAM — with volume down and prices up >70% QoQ — is the cleanest external data point yet on how the AI capex cycle is reshaping the memory stack. Three NAND rivals and Cisco just bought equity to lock in supply.
Read more SemiconductorsTSMC's Global Manufacturing Strategy: From Taiwan to Arizona and Beyond
A strategic analysis of TSMC's geographic diversification, the $100 billion U.S. investment, and why Taiwan will remain one generation ahead in leading-edge nodes.
Read more SemiconductorsThe Technology Behind AI's Packaging Revolution
An accessible deep dive into CoWoS, HBM stacking, and chiplet architectures—the packaging technologies enabling AI infrastructure and why mastering them has become essential for semiconductor leadership.
Read more