CoWoS Capacity and the AI Supply Chain Constraint

Quantifying the Capacity Gap

Understanding the CoWoS bottleneck requires examining specific numbers. TSMC's advanced packaging capacity has grown substantially but demand has grown faster.

Capacity evolution (approximate wafer equivalent units per month):

- 2023: 75,000 units

- 2024: 95,000 units

- Mid-2025: 115,000 units

- 2026 target: 150,000+ units

Customer demand projections through 2026 suggest requirements exceeding 180,000 units monthly, implying a persistent shortfall even as TSMC aggressively expands capacity.

The gap manifests as allocation constraints. Customers cannot order all the AI chips they could sell. NVIDIA, AMD, and hyperscalers building custom silicon all face CoWoS limitations that restrict their product availability.

Why Packaging Is Harder to Scale Than Wafer Fabs

Semiconductor fabs are notoriously capital-intensive and slow to build, typically requiring three to four years from groundbreaking to volume production. Advanced packaging might seem simpler by comparison. It is not.

Several factors constrain packaging capacity expansion:

Equipment availability: Advanced packaging requires specialized tools with limited suppliers. Lithography systems, bonding equipment, and test systems have lead times extending beyond 18 months. Even with unlimited capital, equipment availability constrains expansion speed.

Substrate supply: High-end ABF substrates are essential for CoWoS packages. Substrate capacity takes years to add and has its own supply chain dependencies. Substrate availability has repeatedly limited packaging expansion.

Interposer fabrication: The silicon interposers central to CoWoS are manufactured using semiconductor processes. Interposer capacity requires fab capacity, creating interdependency between packaging expansion and wafer fabrication.

Qualification cycles: Each customer and product requires extensive qualification. New packaging lines cannot simply produce whatever customers order; they must first prove capability for each specific application. These cycles take months.

The NVIDIA Allocation Story

NVIDIA's experience illustrates how CoWoS constraints affect market leaders. During 2023 and 2024, NVIDIA's data center GPU revenue was limited not by demand but by supply.

The company's order backlog extended months into the future. Customers including Microsoft, Google, Amazon, and Meta competed for allocation of products they could not purchase in desired quantities. Cloud providers reportedly committed billions in advance orders to secure supply priority.

NVIDIA management publicly acknowledged supply constraints, noting that packaging rather than wafer fabrication was the limiting factor. The company has worked with TSMC to prioritize its allocation and has reportedly prepaid for capacity to secure supply.

The allocation dynamic affected NVIDIA's product strategy. The company prioritized its highest-margin data center products while limiting supply to gaming and automotive segments. This optimization maximized revenue given constrained supply but left demand unfulfilled across product lines.

Who Else Faces Constraints

NVIDIA's prominence makes its allocation challenges visible, but other companies face similar constraints:

AMD: The company's MI300 series AI accelerators use advanced packaging comparable to NVIDIA's products. AMD has gained share in AI inference applications but faces the same CoWoS capacity limitations as NVIDIA.

Hyperscaler custom silicon: Google's TPU, Amazon's Trainium, and Microsoft's Maia chips all require advanced packaging. These custom silicon programs compete with merchant silicon vendors for limited CoWoS capacity.

Apple: While Apple's M-series chips use different packaging technology (primarily InFO), the company's products still compete for TSMC packaging resources. Apple's enormous volumes command substantial capacity allocation.

Networking chips: High-bandwidth networking silicon for data centers increasingly requires advanced packaging. Broadcom, Marvell, and others face capacity constraints for these products.

The breadth of affected customers underscores that CoWoS constraints are structural rather than company-specific. The entire high-performance computing segment competes for packaging capacity insufficient to meet aggregate demand.

TSMC's Capacity Expansion Plans

TSMC has committed substantial resources to expanding advanced packaging capacity:

Taiwan facilities: The company is adding CoWoS capacity at multiple Taiwan sites, including Taichung and Chiayi. These expansions represent the largest near-term capacity additions.

Amkor partnership: TSMC has partnered with Amkor Technology to add advanced packaging capacity in the United States and potentially other locations. This partnership addresses both capacity constraints and geographic diversification demands.

Equipment investment: TSMC has placed orders for packaging equipment extending years into the future. The company's capital expenditure plans include substantial packaging investments alongside wafer fabrication.

Despite these efforts, capacity additions lag demand growth. TSMC has been transparent that packaging constraints will persist through at least 2026, with meaningful relief dependent on both TSMC's expansion and potentially OSAT partnerships.

The OSAT Alternative

Outsourced Semiconductor Assembly and Test (OSAT) providers offer an alternative to foundry-integrated packaging. Companies including ASE Technology and Amkor Technology have advanced packaging capabilities that could supplement TSMC's capacity.

ASE Technology: As the world's largest OSAT, ASE has invested in advanced packaging to capture overflow demand from foundries. The company's capabilities include interposer-based packaging and 2.5D integration, though at smaller scale than TSMC.

Amkor Technology: Amkor's TSMC partnership gives it a defined role in the CoWoS ecosystem. The company is building capacity specifically to serve TSMC's overflow, with technology transfer ensuring compatibility.

Limitations: OSAT advanced packaging faces qualification barriers. Customers qualified on TSMC's internal packaging lines cannot simply transfer production to OSATs without requalification. This process takes time and creates customer reluctance to split volumes across providers.

The OSAT alternative provides meaningful capacity supplement but cannot fully address the shortage. Foundry-integrated packaging retains advantages in yield, integration, and customer convenience that limit OSAT adoption for the most demanding applications.

When Does Relief Arrive

The timeline for CoWoS capacity relief depends on multiple factors:

2025: Capacity remains tight despite expansion. TSMC's additions help but demand continues growing. Allocation constraints persist for major customers.

2026: Meaningful capacity additions from both TSMC and OSAT partners reach volume production. The gap narrows but may not close completely if AI infrastructure spending continues accelerating.

2027 and beyond: Capacity eventually catches up to demand, assuming AI spending growth moderates. However, new product generations with larger packages and more HBM stacks could maintain supply tightness.

The relief timeline also depends on demand trajectory. If AI infrastructure spending plateaus, current expansion plans could create capacity surplus. If spending accelerates beyond projections, constraints could persist longer than expected.

Implications for Customers and Suppliers

The CoWoS bottleneck creates strategic implications across the value chain:

For chip designers: Packaging availability affects product planning. Designs requiring more CoWoS area face greater supply constraints. Some customers are exploring alternative architectures that reduce packaging requirements.

For cloud providers: AI compute availability depends on packaging as much as chip design. Providers with stronger foundry relationships and larger prepayments secure better allocation. This dynamic advantages larger players.

For equipment suppliers: Packaging equipment demand will remain strong as capacity expands. Companies supplying bonding, lithography, and test equipment for packaging see extended order backlogs.

For materials suppliers: Substrate, underfill, and thermal material suppliers face capacity constraints of their own. The packaging supply chain has multiple potential bottleneck points beyond TSMC's own capacity.

The Structural Nature of the Constraint

The CoWoS bottleneck reflects structural industry dynamics rather than temporary imbalance. Several factors suggest packaging constraints could persist:

Demand trajectory: AI workloads continue scaling, with training runs and inference deployments growing in compute requirements. Each model generation demands more AI chips and thus more packaging capacity.

Architecture trends: Chiplet-based designs and increasing HBM capacity per chip expand packaging area requirements. Future products may require even more CoWoS capacity per chip than current generations.

Capacity concentration: Advanced packaging capable of serving AI applications remains concentrated at TSMC. Alternative suppliers have neither the technology nor the capacity to meaningfully diversify supply.

Capital requirements: Packaging expansion requires substantial investment with long payback periods. Suppliers must balance capacity investment against demand uncertainty, potentially limiting expansion pace.

These dynamics suggest that packaging could remain a supply chain constraint even as the industry invests to expand capacity. The AI infrastructure buildout may persistently push against packaging limits, affecting product availability and industry structure for years to come.